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<title>CMSIS-Core (Cortex-M): SCB_Type Struct Reference</title>
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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.3.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="header">
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<div class="title">SCB_Type Struct Reference</div>  </div>
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<p>Structure type to access the System Control Block (SCB).  
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a21e08d546d8b641bee298a459ea73e46"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46">CPUID</a></td></tr>
<tr class="memdesc:a21e08d546d8b641bee298a459ea73e46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) CPUID Base Register.  <a href="#a21e08d546d8b641bee298a459ea73e46">More...</a><br/></td></tr>
<tr class="separator:a21e08d546d8b641bee298a459ea73e46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">ICSR</a></td></tr>
<tr class="memdesc:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Control and State Register.  <a href="#a0ca18ef984d132c6bf4d9b61cd00f05a">More...</a><br/></td></tr>
<tr class="separator:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a187a4578e920544ed967f98020fb8170"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a187a4578e920544ed967f98020fb8170">VTOR</a></td></tr>
<tr class="memdesc:a187a4578e920544ed967f98020fb8170"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) Vector Table Offset Register.  <a href="#a187a4578e920544ed967f98020fb8170">More...</a><br/></td></tr>
<tr class="separator:a187a4578e920544ed967f98020fb8170"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3e5b8934c647eb1b7383c1894f01380"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">AIRCR</a></td></tr>
<tr class="memdesc:ad3e5b8934c647eb1b7383c1894f01380"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.  <a href="#ad3e5b8934c647eb1b7383c1894f01380">More...</a><br/></td></tr>
<tr class="separator:ad3e5b8934c647eb1b7383c1894f01380"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCR</a></td></tr>
<tr class="memdesc:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) System Control Register.  <a href="#a3a4840c6fa4d1ee75544f4032c88ec34">More...</a><br/></td></tr>
<tr class="separator:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2d6653b0b70faac936046a02809b577f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">CCR</a></td></tr>
<tr class="memdesc:a2d6653b0b70faac936046a02809b577f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) Configuration Control Register.  <a href="#a2d6653b0b70faac936046a02809b577f">More...</a><br/></td></tr>
<tr class="separator:a2d6653b0b70faac936046a02809b577f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85768f4b3dbbc41fd760041ee1202162"><td class="memItemLeft" align="right" valign="top">__IOM uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a85768f4b3dbbc41fd760041ee1202162">SHP</a> [12]</td></tr>
<tr class="memdesc:a85768f4b3dbbc41fd760041ee1202162"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)  <a href="#a85768f4b3dbbc41fd760041ee1202162">More...</a><br/></td></tr>
<tr class="separator:a85768f4b3dbbc41fd760041ee1202162"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7b5ae9741a99808043394c4743b635c4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a7b5ae9741a99808043394c4743b635c4">SHCSR</a></td></tr>
<tr class="memdesc:a7b5ae9741a99808043394c4743b635c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) System Handler Control and State Register.  <a href="#a7b5ae9741a99808043394c4743b635c4">More...</a><br/></td></tr>
<tr class="separator:a7b5ae9741a99808043394c4743b635c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0cda9e061b42373383418663092ad19a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a0cda9e061b42373383418663092ad19a">CFSR</a></td></tr>
<tr class="memdesc:a0cda9e061b42373383418663092ad19a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) Configurable Fault Status Register.  <a href="#a0cda9e061b42373383418663092ad19a">More...</a><br/></td></tr>
<tr class="separator:a0cda9e061b42373383418663092ad19a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a14ad254659362b9752c69afe3fd80934"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a14ad254659362b9752c69afe3fd80934">HFSR</a></td></tr>
<tr class="memdesc:a14ad254659362b9752c69afe3fd80934"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x02C (R/W) HardFault Status Register.  <a href="#a14ad254659362b9752c69afe3fd80934">More...</a><br/></td></tr>
<tr class="separator:a14ad254659362b9752c69afe3fd80934"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a191579bde0d21ff51d30a714fd887033"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a191579bde0d21ff51d30a714fd887033">DFSR</a></td></tr>
<tr class="memdesc:a191579bde0d21ff51d30a714fd887033"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x030 (R/W) Debug Fault Status Register.  <a href="#a191579bde0d21ff51d30a714fd887033">More...</a><br/></td></tr>
<tr class="separator:a191579bde0d21ff51d30a714fd887033"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a2d03d0b7cec2254f39eb1c46c7445e80">MMFAR</a></td></tr>
<tr class="memdesc:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x034 (R/W) MemManage Fault Address Register.  <a href="#a2d03d0b7cec2254f39eb1c46c7445e80">More...</a><br/></td></tr>
<tr class="separator:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c">BFAR</a></td></tr>
<tr class="memdesc:a3f8e7e58be4e41c88dfa78f54589271c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x038 (R/W) BusFault Address Register.  <a href="#a3f8e7e58be4e41c88dfa78f54589271c">More...</a><br/></td></tr>
<tr class="separator:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab65372404ce64b0f0b35e2709429404e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e">AFSR</a></td></tr>
<tr class="memdesc:ab65372404ce64b0f0b35e2709429404e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x03C (R/W) Auxiliary Fault Status Register.  <a href="#ab65372404ce64b0f0b35e2709429404e">More...</a><br/></td></tr>
<tr class="separator:ab65372404ce64b0f0b35e2709429404e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a681c9d9e518b217976bef38c2423d83d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a681c9d9e518b217976bef38c2423d83d">PFR</a> [2]</td></tr>
<tr class="memdesc:a681c9d9e518b217976bef38c2423d83d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x040 (R/ ) Processor Feature Register.  <a href="#a681c9d9e518b217976bef38c2423d83d">More...</a><br/></td></tr>
<tr class="separator:a681c9d9e518b217976bef38c2423d83d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">DFR</a></td></tr>
<tr class="memdesc:a85dd6fe77aab17e7ea89a52c59da6004"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x048 (R/ ) Debug Feature Register.  <a href="#a85dd6fe77aab17e7ea89a52c59da6004">More...</a><br/></td></tr>
<tr class="separator:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af084e1b2dad004a88668efea1dfe7fa1"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1">ADR</a></td></tr>
<tr class="memdesc:af084e1b2dad004a88668efea1dfe7fa1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x04C (R/ ) Auxiliary Feature Register.  <a href="#af084e1b2dad004a88668efea1dfe7fa1">More...</a><br/></td></tr>
<tr class="separator:af084e1b2dad004a88668efea1dfe7fa1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa11887804412bda283cc85a83fdafa7c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#aa11887804412bda283cc85a83fdafa7c">MMFR</a> [4]</td></tr>
<tr class="memdesc:aa11887804412bda283cc85a83fdafa7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x050 (R/ ) Memory Model Feature Register.  <a href="#aa11887804412bda283cc85a83fdafa7c">More...</a><br/></td></tr>
<tr class="separator:aa11887804412bda283cc85a83fdafa7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ae0136a2d2d3c45f016b2c449e92b2066">ISAR</a> [5]</td></tr>
<tr class="memdesc:ae0136a2d2d3c45f016b2c449e92b2066"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x060 (R/ ) Instruction Set Attributes Register.  <a href="#ae0136a2d2d3c45f016b2c449e92b2066">More...</a><br/></td></tr>
<tr class="separator:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ac89a5d9901e3748d22a7090bfca2bee6">RESERVED0</a> [5]</td></tr>
<tr class="memdesc:ac89a5d9901e3748d22a7090bfca2bee6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#ac89a5d9901e3748d22a7090bfca2bee6">More...</a><br/></td></tr>
<tr class="separator:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac6a860c1b8d8154a1f00d99d23b67764"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764">CPACR</a></td></tr>
<tr class="memdesc:ac6a860c1b8d8154a1f00d99d23b67764"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x088 (R/W) Coprocessor Access Control Register.  <a href="#ac6a860c1b8d8154a1f00d99d23b67764">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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          <td class="memname">__IM uint32_t SCB_Type::ADR</td>
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